Solving AI DC Power Challenges with Advanced Packaging
Advanced packaging solves AI data center power challenges by enabling vertical power delivery to computing chiplets, memory, and switches. These innovations reduce resistive losses, shorten electrical paths, and improve thermal dissipation. Miniaturization is possible when advanced packaging that integrates passives, as well as WBG (e.g. GaN) devices for high efficiency of voltage conversion.
Vertical power delivery resolves AI hardware power bottlenecks by routing current vertically from voltage regulators positioned directly underneath the processor die, rather than laterally across the motherboard. This vertical architecture shortens electrical paths from centimeters to millimeters, drastically reducing resistance and power losses (I²R) for chips demanding over 1,000 amperes. By eliminating lateral power routing, VPD also frees up valuable perimeter space on the silicon for high-bandwidth memory (HBM), while simultaneously stabilizing voltage delivery and minimizing noise at the transistor layer.
Future generation of power solution, called Integrated Voltage Regulation (IVR), may integrate the power devices inside of the CoWoS structure. It makes possible for even higher efficiency of power conversion and conversion.
Key Technologies Covered
- Advanced Packaging
- Power Integrity (PI)
- Vertical Power Delivery (VPD)
- Voltage Regulator Module (VRM)
- Resistive Power Loss (I²R)
- On-Package Capacitors