Mixx Technologies Inc

Mr. Vivek Raghuraman, CEO, Cofounder, Mixx Technologies Inc

Vivek is the co-founder and CEO of Mixx Technologies, a deep-tech startup pioneering high-density interconnects for AI and high-performance computing. With over 20 years in the semiconductor industry, he’s launched groundbreaking products, including the first co-packaged optics at Broadcom and a silicon photonics transceiver at Intel. Holding seven patents, Vivek is an internationally recognized expert in silicon photonics and advanced packaging, advising the U.S. Department of Energy’s ARPA-E program, IEEE steering committee for photonics, the India Semiconductor Mission, and the Semiconductor Research Council's MAPT program, shaping the future of semiconductor technologies.

 

 

 

Topic:

Full Stack Wafer-Level Silicon Photonics for Next-Gen AI Infrastructure

 

Abstract:

Active alignment (AA) remains the primary yield and throughput bottleneck in silicon photonics packaging. Batch-to-batch variation in fiber array units (FAUs) makes AA inherently unpredictable at scale, constraining units-per-hour output and limiting the density achievable in co-packaged optical architectures. This paper presents Mixx Technologies' wafer-level stacking approach, which eliminates AA entirely across all product lines through wafer-to-wafer fusion bonding and chip-to-wafer hybrid bonding. The resulting optics-to-silicon interface achieves a fully repeatable, epoxy-free structure with controlled bond-line thickness (BLT), supporting both grating coupling and edge coupling configurations. At the system level, these packaging advances are unified within the HBxIO™ architecture — a full-stack interconnect platform that delivers a radix of 256, reach exceeding 500 meters, I/O density greater than 10 Tb/mm, 20x latency reduction, and 75% power savings versus pluggable optical baselines. HBxIO™ disaggregates compute resources under a single fungible architecture, reducing projected AI infrastructure energy demand by 72%.

 

Key Technologies Covered: 

  • Wafer-to-wafer fusion bonding for optics-to-silicon integration 
  • Chip-to-wafer hybrid bonding for heterogeneous optical-electronic assembly 
  • Wafer-level stacking as a replacement for active alignment (AA) in photonics packaging 
  • Controlled bond-line thickness (BLT) engineering for repeatable, epoxy-free interfaces 
  • Grating coupling configurations for optics-to-silicon interconnect 
  • Edge coupling configurations for optics-to-silicon interconnect 
  • HBxIO™ full-stack interconnect architecture for co-packaged optics 
  • High-radix, long-reach optical interconnect design 
  • Low-latency, power-efficient optical I/O architecture 
  • Disaggregated, fungible compute architecture for AI infrastructure efficiency