ANIAH SAS

Mr. Allen (Wei-Ting) Chen, Director of Applications Engineering & Business Development, APAC, ANIAH SAS

Allen Chen is a seasoned professional with 15 years of experience in the IC and EDA industry, currently serving as Director of Applications Engineering & Business Development, APAC at Aniah. He previously specialized in foundry technology support at Synopsys and Siemens EDA, and facilitated real-world tape-out projects at HiSilicon. At Aniah, he supports leading IC design houses with ERC sign-off on advanced process nodes and drives business development across the APAC region. His primary focus is leveraging AI to optimize IC design flows and spearhead innovation in the EDA field.

 

 

Topic:

One Platform for Tape-Out ERC: OneCheck + Amigo AI for Trusted Mixed-Signal Verification

 

Abstract:

Advanced mixed-signal tape-out is bottlenecked by expert review, not tool runtime. ERC warnings, false positives, incomplete simulations, and analog edge cases make sign-off slow and risky. This talk presents One Platform — OneCheck + Amigo AI — a new approach to trusted mixed-signal verification. OneCheck performs exhaustive, vector-less electrical rule checking across all power states and voltage domains, building a formal semantic circuit model that catches corner cases simulation misses. Amigo AI, a grounded design agent, turns that verified context into plain-language explanations, automatically generated SPICE testbenches, numeric evidence, and reusable review memory — without ever prompting on raw netlists. We share industrial validation results across advanced-node blocks (TSMC N7 to A16), real true-positive sign-off escapes caught before tape-out, and how expert ERC review becomes a repeatable, scalable verification workflow for first-time-right silicon.

Key Technologies Covered:

  • Vector-less formal electrical rule checking (ERC) — no testbenches, no simulation wait
  • Exhaustive all-power-state and all-voltage-domain analysis (100% reachable-state coverage)
  • Hierarchical netlist verification scaling to 1B+ devices — minutes per block
  • Smart violation clustering — 10K+ raw violations reduced to ~50 root causes
  • Grounded AI design agent (Amigo AI) reasoning over a formal semantic circuit model
  • Bounded-context AI safety: no raw-netlist prompting, evidence-backed answers only
  • Automatic SPICE testbench generation for numeric verification of findings
  • Reusable review memory: waiver history and cross-project violation signatures
  • Cadence Virtuoso integration with schematic cross-probing
  • Production validation on advanced nodes: TSMC N7, N5, N3P, and A16