Heterogeneous Integration Roadmap (HIR)

上午 10:00 - 上午 10:30

Heterogeneous Integration (HI) — the integration of separately manufactured components into a higher-level System-in-Package delivering enhanced functionality and improved operating characteristics — is now central to continued advances in computing and communications. Sustaining this trajectory requires advanced packaging to scale along multiple vectors simultaneously, and, as argued in Nature Reviews Electrical Engineering (Mahajan, Chen, Thompson, et al., 2026), depends on comprehensive roadmaps that align systems architects, packaging specialists, and semiconductor technologists to common goals. Systematic road-mapping is needed both to mature the correct building blocks in advance of demand and to expose integration challenges that are complex, time-consuming, and frequently under-scoped.

This paper presents the Heterogeneous Integration Roadmap (HIR), a volunteer-driven, open-access, systems-application-driven effort blending market pull with technology push. We describe its four-part structure: target systems (HPC/AI and data centers, mobile, aerospace and defense, medical, autonomous automotive, IoT, with space electronics newly added); building blocks spanning integrated photonics, power electronics, MEMS/sensors, and 5G/6G+ mixed-signal integration; technology integration areas including SiP, 2D/3D interconnects, and wafer- and panel-level packaging; and cross-cutting technical areas, including a new metrology chapter. We report the 2025 Edition's 25 updated chapters and the accelerated 2026 schedule.

Key Technologies Covered

Building blocks: photonics, power, MEMS, 5G/6G+
Integration platforms: SiP, 3D interconnects, wafer/panel packaging
Technical areas: materials, thermal, co-design, new metrology
Driving systems: AI/HPC, mobile, automotive, IoT, space

Featured Speakers

Mr. Steven Duggan

Senior Principal Engineer, Intel

Steven Duggan is a Senior Principal Engineer specializing in the development and industrialization of advanced semiconductor packaging equipment. He has deep domain expertise spanning high-density 2.5D/3D silicon integration, advanced die-to-die interconnects, and backside power delivery technologies. Since 1995, Steven has held diverse engineering and supply chain leadership roles across silicon fabrication, technology development, and high-volume assembly and test manufacturing.

Throughout his career, he has led first-of-a-kind equipment engagements, establishing novel process capabilities for flip-chip and wafer-level assembly processes. His expertise lies in defining equipment architectures, maturing process capabilities, and retiring technical risks from early feasibility to high-volume manufacturing. Previously, Steven managed a 26-person R&D and capital commodity organization, driving global equipment strategy, supplier alignment, and lifecycle asset management. He is recognized for combining deep technical execution with cross-functional leadership to scale advanced packaging roadmaps.