Keynote: Testing at Scale for the AI Era: From Silicon Complexity to System-Level Reliability

上午 9:40 - 上午 10:20

AI is redefining the boundaries of semiconductor compute—and with them, the role of testing. Advanced process nodes, chiplets, HBM, 2.5D/3D integration, high-speed interconnects, rising power density, and emerging optical connectivity are transforming AI accelerators from individual devices into highly integrated compute systems. As compute continues to scale from silicon to packages, racks, and AI factories, test complexity is growing even faster than transistor complexity.

This evolution creates a fundamental challenge: how can the industry deliver greater test coverage and reliability confidence without allowing test time and cost to scale at the same rate as complexity? At the same time, the definition of a “good” device is changing. Traditional semiconductor test has focused on screening out defective devices. In increasingly complex AI systems, however, passing a test is necessary but no longer sufficient. Margin, HBM and advanced-package interactions, power and thermal behavior, high-speed connectivity, and workload-dependent failure mechanisms increasingly determine whether a device will remain reliable in real-world operation.

At AI scale, this challenge extends beyond device quality. Rare component-level failures can become significant system- and fleet-level events, shifting the focus from quality at shipment to reliability over time—and ultimately from whether a system can run to whether its computation can be trusted.

This keynote examines how testing must evolve alongside the compute roadmap: from defect screening to intelligent test optimization, from device-level validation to system-level reliability, and from isolated test data to closed-loop learning across the product lifecycle. As the boundary of compute expands, the boundary of test must expand with it.

The next chapter of semiconductor testing is not simply about finding failures. It is about building confidence—and making reliable compute scalable.

 

Key Technologies Covered

  • Redefine the Architecture of Compute
  • Test Complexity is Multiplying
  • Reliability Becomes the Product

Featured Speakers

Mr. Morris D.Y. Chang

張登堯

副總經理, 京元電子股份有限公司

Morris D.Y. Chang is Vice President of the Business Center at KYEC, where he leads cross-functional business and engineering organizations responsible for revenue growth, strategic customer partnerships, new product introduction (NPI), and advanced test solution development. With more than 25 years of experience in the semiconductor industry, Morris has built extensive expertise in semiconductor testing, business development, and technology commercialization. After spending 19 years with KYEC, he joined Intel Microelectronics Taiwan in 2022, where he served for two years before returning to KYEC in 2024. Prior to joining KYEC in 2003, Morris worked as a Senior Test Engineer at Philips Electronics Singapore.

 

Throughout his career, Morris has worked closely with global customers and engineering teams to transition complex semiconductor products from development into high-volume manufacturing, with a focus on improving yield, reducing test cost, and developing robust and scalable test solutions for increasingly complex semiconductor devices.

 

Morris holds an M.S. in Information and Electronic Engineering from National Central University in Taiwan and an M.S. in Finance from the City University of New York (CUNY).