AI at Scale: Breaking the Energy Wall with HI
As AI enters its most demanding compute era, system performance is no longer limited by transistor scaling, but by interconnect energy and data movement. This fundamental shift elevates system-level design and positions heterogeneous integration as the critical engine to sustain AI scaling.
This talk explores how advanced packaging innovations are redefining the AI roadmap by enabling shorter interconnects, higher I/O density, and dramatically lower energy per bit. Together, these advances unlock significant gains in bandwidth, power efficiency, and overall system performance. A key focus will be vertical interconnect scaling through fine-pitch hybrid bonding and die-to-wafer (D2W) integration, which are rapidly becoming foundational for next-generation AI architecture.
As D2W pitches continue to shrink, scaling challenges move beyond individual processes to full integration complexity. Achieving high yield and performance demands tight co-optimization across materials, processes, and design, with critical focus on defectivity reduction, overlay precision, and stress control.
The presentation will also introduce reconstituted D2W integration as a scalable pathway for high-volume manufacturing of advanced AI systems. By combining architectural innovation with deep process co-optimization, heterogeneous integration extends system scaling beyond traditional limits and enables the next wave of AI performance growth.
Key Technologies Covered
- Heterogeneous integration for AI system scaling
- Hybrid bonding & Die-to-Wafer (D2W) for high-density interconnects
- Reconstituted D2W & co-optimization for manufacturability
