As semiconductor scaling evolves, what is the role of High-NA EUV lithography?
While the pace of classical dimensional scaling is moderating, performance targets for advanced technology nodes continue to accelerate, placing increasing demands on patterning, integration, and system-level optimization.
The introduction of High-NA EUV provides the resolution and patterning capabilities required to support future semiconductor roadmaps. As the industry pushes toward ever more ambitious performance and density targets, realizing the full value of these capabilities requires continued innovation across the ecosystem, including materials, patterning approaches, metrology, and design-technology co-optimization.
This talk will present key High-NA patterning results obtained at imec and discuss what they reveal about the future of semiconductor scaling. It will highlight how High-NA extends the industry's scaling toolbox and enables new pathways for continued progress, while underscoring the importance of close collaboration across the ecosystem to translate technological advances into manufacturable solutions.
The evolution of semiconductor scaling is not reducing the importance of patterning innovation. Rather, it is elevating its role within a broader framework of technology and system optimization, where High-NA EUV serves as a key enabler for sustaining future generations of performance scaling.
Key Technologies Covered
- High-NA EUV lithography (0.55 NA)
- Advanced semiconductor patterning
