Opening Keynote: Scaling the Agentic AI Era with Advanced Packaging, Heterogeneous Integration, and Optical Interconnects

上午 9:35 - 上午 10:05

As AI systems scale beyond the limits of traditional transistor-driven progress, advanced packaging and heterogeneous integration have become foundational to the next era of compute. AMD has been at the forefront of this transition—leading the industry from chiplet architectures to 2.5D, 3D hybrid-bonded, and 3.5D system integration approaches that optimize power, performance, area, and cost while enabling increasingly complex AI architectures.

This keynote will examine how the center of innovation is shifting from the die alone to the full system stack: compute, memory, interconnect, package, board, rack, and the manufacturing ecosystem required to bring them together. It will highlight the architectural and technology co-optimization needed to compose large multi-die systems, scale bandwidth efficiently, and manage the growing electrical, thermal, mechanical, and cost challenges of AI infrastructure. The session will also explore the next frontier in system scaling through optical interconnect technologies, including co-packaged optics and silicon photonics, as critical enablers for low-power, high-bandwidth communication at rack and datacenter scale.

Finally, the talk will show how AMD is not only building the hardware foundation for the agentic world, but also transforming how that hardware is created—deploying agentic AI internally across package design, modeling, analytics, and engineering workflows to accelerate multi-physics co-design, improve execution efficiency, and shorten time-to-solution. Together, these advances point to a new model for innovation: one where breakthroughs in architecture, packaging, optics, software, and AI-enabled engineering all move in lockstep to scale the future of intelligent systems.

Key Technologies Covered

Chiplet-Based Architectures with 2.5D, 3D, and 3.5D Integration
Hybrid-Bonded Multi-Die Integration
System-Level Co-Optimization Across Compute, Memory, and Interconnect
Scalable Multi-Die System Composition and Bandwidth Scaling
Electrical, Thermal, Mechanical, and Cost Constraint Management
Optical Interconnects with Co-Packaged Optics and Silicon Photonics
Low-Power, High-Bandwidth Rack- and Datacenter-Scale Communication
Agentic AI–Driven Multi-Physics Co-Design and Engineering Workflows

Featured Speakers

Dr. Raja Swaminathan

Corporate Vice President, Advanced Micro Devices

Dr. Raja Swaminathan is Corporate Vice President of Heterogeneous Integration Technologies at AMD, where he leads the company’s advanced packaging and heterogeneous integration roadmap. He also oversees Optics technology development, driving innovation in high‑speed optical interconnects and photonics integration.

With a distinguished career spanning Intel, Apple, and AMD, Dr. Swaminathan brings deep expertise in design‑technology co‑optimization and a strong focus on optimizing power, performance, area, and cost (PPAC). His contributions have enabled several industry‑defining technologies, including EMIB, Apple’s M‑series packaging, AMD 3D V‑Cache™, and 3.5D architectures for AI accelerators.

Dr. Swaminathan holds a PhD from Carnegie Mellon University and an undergraduate degree from IIT Madras. He is the inventor or co‑inventor on over 100 patents and the author of more than 40 technical publications. Recently named an IEEE Fellow, he also serves as a technical advisor to multiple startups. Beyond his technical leadership, Dr. Swaminathan shares insights on leadership and life lessons drawn from the semiconductor industry on LinkedIn.