Keynote: Challenges and Opportunities for Metrology and Inspection of Advanced Packaging

上午 9:45 - 上午 10:25

As industry is marching to one trillion transistors chips with multiple frontlines of innovations, Advanced Packaging (AP) plays a big role through 2.5D and 3D integration. Metrology and Inspection become more critical as the integration processes become more complicated with larger and more components being assembled. This presentation will share the challenges of metrology and inspections during those integrations such as DRAM/HBM damage concern by X-ray, Infrared Red (IR) limitation to look through transparent materials only, higher warped wafers to handle and resolution constraints for Scanning Acoustic Microscope etc. Opportunities will be shared in different aspects: 1) combine the more advanced computer power/AI models; 2) work with Foundry customers, partners like HBM vendors, equipment vendors as alliance; 3) design for metrology (DfM), 4) import new technologies from other industries etc.

 

Key Technologies Covered

  • Surace defect detection
  • Buried defects
  • 2D and 3D Xray
  • Scanning acoustic microscope
  • Atomic Force Microscope
  • Warpage
  • Design for Metrology (DFM)

Featured Speakers

Dr. Zhihua Zou

鄒志華博士

處長, 台積公司

Received his B.Sc. and M.Sc. In Precision Instrument Department from Tianin University in China, and his M.Sc. in Computer Science and Ph.D. in Mechanical Engineering from University of North Carolina at Charlotte USA. He worked as technology Engineering manager at Intel in the assembly and Test Development Department, mainly developing metrology and test solutions for HDI substrates and Flip Chip packaging including Embedded Bridge (EMIB) over 18 years, as Principal Engineer developing the hybrid bonding solutions over 2 years prior to joining TSMC 2023. Currently he is a director leading Advanced Packaging Metrology Engineering (APME) Division at APTS (Advanced Packaging Test Service) of TSMC, responsible for mass production of all Metrology related across Advanced Packaging Technologies covering InFo, CoWoS and SoIC etc. He held 15 patents in metrology and material areas.