Heterogeneous Large Scale Integration (HLSI) driving logic scaling to CMOS 2.0

With the rise of 2.5D and 3D integration, advanced compute systems are increasingly scaled through the co-optimization of heterogeneous technologies. This shift has led to the emergence of co-design approaches across technology dies that were traditionally developed in isolation. When combined with the right architectural innovations, such co-optimization can deliver substantial performance gains required by future AI systems. This paradigm can be extended further down to the CMOS platform itself. While the general-purpose nature of CMOS has long been a key driver of its success, it is gradually becoming a limitation. Modern systems demand transistors that are simultaneously compact, energy-efficient, and high-performance across a wide range of functions—often within the same system-on-chip (SoC). A promising solution lies in disaggregating these functions across multiple active layers, each implemented with a technology optimized for its specific role. By leveraging this form of heterogeneity, a new scaling approach emerges—ushering in what can be described as the “CMOS 2.0” era.