Future metrology challenges, the necessary evil
Often perceived as a cost, a constraint, or a bottleneck, metrology has historically been a supporting function to enable scaling. At advanced nodes, metrology is becoming the central enabler of performance, yield, and system integration.
Metrology challenge is increasingly defined by what is difficult to access, both optically and geometricall: buried interfaces, nanosheet and CFET architectures, backside alignment, and thick or reconstructed wafers. It pushes conventional techniques to their limits and demand new approaches that combine multiple probing modalities, modeling, and data-driven inference.
For High-NA EUV lithography we need to control edge placement, focus, overlay, stochastic defects, and full 3D profile simultaneously.
This paradigm shift is even more pronounced in advanced packaging and 3D integration, where metrology moves from process monitoring to direct impact on functionality. Here, bond integrity, interconnect alignment, yield, and ultimately system performance is intrinsically linked to the ability to measure and control structures beyond the front-end domain.
This talk will explore why metrology is becoming the critical key for scaling and system integration and will require a fundamental rethinking of how we measure, model, and control semiconductor processes.
Key Technologies Covered
- Metrology challenges
- How new architectures (CFET, Bonding) are changing metrology
