Heterogeneous Integration Global Summit 2026 – Day 1

AI / HPC have been the main driving horse to propel the unprecedented strong growth of semiconductor technology industry and market applications. In the past few years, AI/ HPC industry leaders, including AI chip designers and CSP, continue to invest massive resources to design next generation AI accelerators and advanced system integration technology in large reticle size aiming at increasing the compute throughputs and memory bandwidth at low energy consumption (aka high energy efficiency performance, EEP). Looking forward, the advanced packaging development for the next decade focuses on four directions: 1) More adoption of chiplets technology in 3DIC for cost, yield and performance. 3DIC (aka SoIC) tightly integrates chiplets in compact form enabling inter-chips high interconnect density for high bandwidth density and EEP, which is essential to hyperscale datacenters running large AI models, 2) More compute/3DIC and HBMs integration on a 2.5D package for AI inference, 3) More System Technology Co-optimization (STCO) to optimize the power supply architecture (aka eDTC, IVR) and thermal management (aka Lid/TIM + coldplate liquid cooling) at the system level to improve system-level EEP, 4) More Co-Packaged Optics (CPO) on datacenter network switch and on rack AI compute. CPO significantly increases the inter-AI logics (aka GPUs-to-GPUs, ASICs-to-ASICs) data transmission bandwidth at distance while reduces energy consumption and latency, making clusters of AI compute with coherency possible