SiliconMind

Mr. Mu-Chi Chen, CEO, SiliconMind

Mu-Chi Chen brings cross-national AI R&D experience to his work, with a background spanning UC Berkeley, Silicon Valley, Mohamed bin Zayed University of Artificial Intelligence, Academia Sinica, and National Taiwan University. His research focuses on efficient LLM inference and the application of reasoning-oriented SFT, RLVR, and multi-agent data pipelines across the IC design flow. Central to his work is a simple conviction: a company's AI should be its own. When AI is sovereign customer-owned, running in-house, and continuously trained on proprietary design data — every project makes it smarter, and that accumulated intelligence stays home, compounding into a lasting competitive edge rather than flowing outward to strengthen someone else's model.

 

 

 

 

 

Topic:

SiliconMind — The Chip AI Factory: Private, On-Premise AI Agents for Autonomous IC Design

 

Abstract:

Custom-silicon demand is accelerating across AI, automotive, robotics, and networking, but the industry cannot hire its way out of the resulting RTL design-and-verification bottleneck — and cloud AI tools force design teams to expose their most sensitive IP to third-party models. SiliconMind, a Taiwan-based IC AI foundry spun off from National Taiwan University and Academia Sinica, takes a different path: private, on-premise AI trained and continuously improved on the customer's own design data, expert feedback, and internal workflows, so that the AI — and the design knowledge inside it — belongs to the customer. 

 

This talk presents SiliconMind-V1, a family of small (4–8B) open-source models that, through multi-agent distillation and debug-reasoning workflows, learn the full RTL flow of code generation, testbench-driven verification, and debugging. Despite their size, they match or exceed models more than 100× larger on industry benchmarks such as VerilogEval-v2 and Nvidia's CVDP. We show how an agentic harness turns these models into an autonomous design loop, how evolutionary RTL mutation delivers measurable Power–Performance–Area gains, and how a vision-guided extension reads multimodal specifications — schematics, waveforms, tables — to generate high-quality RTL. We close with our roadmap from spec-to-verified-RTL toward spec-to-GDSII, and a view of chip design as an AI-native discipline built on infrastructure the customer owns rather than rents.

 

Key Technologies Covered:

  • Multi-agent distillation — Code / Test / Debug agents generate reasoning data to train small models on the full RTL workflow 
  • Small, efficient on-premise open-source models (4–8B SiliconMind-V1, built on Qwen3 / Olmo-3) 
  • Agentic harness for tool calling — testbench-driven design refinement with iterative ebug-reasoning loops and parallel branch exploration 
  • Test-time scaling / search-based reasoning for functional correctness and design-space exploration