Enabling High-Performance and Reliable RDL Interconnects through Controlled Large Via Copper Filling in Advanced Packaging

Advanced semiconductor packaging increasingly relies on multilayer redistribution architectures to support higher routing density, heterogeneous integration, and improved package-level electrical performance. Recent industry developments indicate a growing reliance on RDL-based interconnect concepts in advanced platforms such as CoWoS, where RDL layers are expected to play a key role in future implementations (e.g., CoWoS-R). At the same time, alternative vertical interconnect concepts such as stacking vias are facing limitations due to stress-related reliability challenges. In this context, large copper-filled vias play a critical role as vertical interconnects between metallization levels, providing not only reliable signal, power, and ground routing but also enabling low-resistance current paths and enhanced thermal dissipation, which are essential for high-performance semiconductor applications.

This presentation discusses the electrochemical mechanism of large via fill in advanced RDL packaging, with a focus on deposition profile control. For large and shallow via structures, successful filling is governed by the ability to control where and how copper grows during electrodeposition. In addition, achieving high plating uniformity across the wafer is of critical importance, as non-uniform deposition can lead to significant variability in via fill behavior and ultimately impact device performance and yield. The process must therefore enable efficient metallization of the via while limiting dimpling, excessive overburden, rim overplating, and layout-dependent profile variations.

RDL plating performance - particularly via filling and overall plating uniformity - is governed by the interaction of current distribution, mass transport, and organic additives. Uniformity across different feature densities and wafer locations is a key requirement to ensure consistent via profiles and reliable interconnect formation. The careful design and balance of accelerator, suppressor, and leveler components are crucial for tuning local deposition rates both within the via and on the surrounding surface. This presentation highlights how these additive-driven mechanisms can be leveraged to precisely control via filling performance evolution while simultaneously achieving high plating uniformity, ultimately enabling optimized large via fill processes for reliable vertical interconnect formation in advanced semiconductor packaging.

Key Technologies Covered

• Multilayer RDL packaging architectures
• Large copper via filling
• Electrochemical copper deposition processes
• Additive chemistry deposition control
• Via fill profile optimization