Integration of 2D Materials for Advanced Logic Scaling
The continued scaling of silicon-based CMOS is increasingly constrained by fundamental electrostatic limits, motivating the exploration of alternative channel materials and device architectures. Two-dimensional (2D) semiconductors, particularly transition metal dichalcogenides (TMDs), offer a compelling pathway to extend logic scaling beyond these limits.
The handling, transfer, and integration of ultra-thin, mechanically fragile layers present significant manufacturing challenges. A key challenge lies in the sequential integration of multiple 2D layers without compromising the integrity of previously fabricated device tiers. Direct high-temperature growth techniques such as chemical vapor deposition (CVD), while suitable for high-quality 2D material synthesis, can degrade underlying layers.
To address this limitation, heterogeneous integration through low-temperature transfer methods have has been explored. In this approach, individual 2D layers are first synthesized independently on optimized donor substrates at elevated temperatures (>800 °C) to ensure high crystalline quality. These layers are then transferred and stacked onto target wafers at reduced temperatures, preserving the structural and electronic properties of both the transferred material and the underlying device layers.
This work highlights how established semiconductor packaging solutions—specifically temporary bonding and debonding (TBDB) materials traditionally used for wafer support during back grinding—can be repurposed to address these challenges. Leveraging proven TBDB platforms, this study explores their application in the transfer of 2D materials, enabling precise handling and integration into device structures.
Key Technologies Covered
- 2D Materials
- Heterogenous integration
- Thin layer transfer
- Temporary bonding/ debonding
