Keynote: Advanced Packaging Technologies: Enabling Next-Generation Heterogeneously Integrated AI Systems

2:00 pm - 2:25 pm

The rapid growth of Generative AI and high-performance computing (HPC) demands higher compute power which is driving integration of chiplets at package level to realize the advanced compute systems with Trillion transistors. System-in-package (SiP) scaling enables the long-term roadmap for continued power, performance, form-factor and cost optimization of HPC-systems. A system-in-package (SiP) typically integrates multiple heterogeneous chiplets namely, xPU, Memory, and I/O chiplets, and, hundreds to thousands of such SiPs are interconnected in servers and racks across a hyper-scale data centre to deliver exascale to zettascale compute performance to support the rapidly growing demands of generative AI applications over the coming decade. Advanced packaging platforms are fundamental to realizing these highly complex, heterogeneous multi-chiplet systems. The effectiveness of chiplet integration depends critically on achieving high-density, high-bandwidth, and energy-efficient interconnects that enable seamless communication among chiplets within the SiP. As a result, innovations in packaging architecture, interconnect technologies, and heterogeneous integration have become essential for the continued evolution of AI and HPC systems. In this presentation, we will explore the latest advances in advanced packaging technologies and interconnect scaling being developed at IME to enable industry pathfinding, design, fabrication, assembly, and prototyping of heterogeneous multi-chiplet SiPs for AI and HPC applications. The talk will also highlight how IME’s collaborative R&D model brings together stakeholders across the semiconductor value chain—from materials and equipment suppliers to design houses, foundries, OSATs, and system companies—to accelerate innovation and the translation of advanced packaging technologies into next-generation AI computing systems.

Key Technologies Covered

Advanced Packaging technologies and Interconnects scaling for heterogenous integration
Ultra large high density fan-out wafer level packaging
W2W/C2W hybrid bonding for chip stacking
Co-Packaged Optics packaging technology and roadmap
Thermal solutions for high power complex system

Featured Speakers

Dr. Yoon SU

Program Director, A*STAR, Singapore

Dr. SU Yoon serves as Program Director at the Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore. He brings over 30 years of distinguished experience spanning R&D Institute, IDM, and OSAT sectors, with deep expertise in semiconductor packaging materials and advanced packaging technologies.

His current research centers on wafer- and panel-level packaging, co-packaged optics (CPO), quantum device packaging and 2.5/3D heterogeneous integration — technologies that are instrumental in enabling next-generation AI and HPC systems.

He holds a Ph.D. and Master's degree in Materials Science and Engineering and an MBA degree. Over the course of his career, he has held diverse R&D and senior management positions in NMCs.

A prolific contributor to the field, he has authored and co-authored more than 300 journal and conference publications, delivered numerous keynote speechs and invited talks, and holds over 30 US patents. He was also an active member of the international microelectronics community, having served as a board member, committee member, organizer, and reviewer for leading conferences and professional bodies including SEMI, EPTC, ESTC, iMAPS, UCIe and ISES/ISIG.