From Gigawatts to Tools: Sizing the AI Build-Out's Demand for Wafer Fab Equipment
The AI infrastructure build-out is typically measured in gigawatts of compute that are set to be deployed over the coming decade. For the equipment, materials and manufacturing industry, the task is translating those headline gigawatt figures into a realistic plan for the wafer capacity, equipment and tooling the build-out requires.
This session presents a bottom-up framework that traces AI demand from gigawatts of deployed compute, through accelerators, their memory and logic content, and the wafer capacity they require, down to wafer fab equipment spending by segment.
It starts by separating announced gigawatts from the capacity that can realistically be energized and brought online, using a bottom-up data-center model, then sizing the bottlenecks that determine how quickly that demand can be met. The aim is to give capacity decision-makers a demand-anchored way to stress-test their own assumptions: where AI demand converts into durable tool demand, and where the real bottlenecks lie, from advanced packaging and DRAM capacity to EUV.
Key Technologies Covered
- GWs to wafer fab equipment (WFE)
- AI accelerator and custom-silicon (GPU/ASIC)
- HBM and DRAM
- Advanced packaging (CoWoS / 2.5D-3D)
- EUV lithography
- Leading-edge logic