Next Step-Function Change in AI Data Center Power Delivery - IVR Power Chiplets into xPU Package

2:00 pm - 2:25 pm

The rapid growth of artificial intelligence workloads is pushing data center processors toward multi-kilowatt power levels, making conventional board-level voltage regulation increasingly inefficient. Power delivery is becoming the showstopper for AI performance scaling.

This talk will discuss how the last stage point-of-load voltage regulation causes the power overhead to reach more than twice the power of the core compute. Furthermore, we illustrate how moving voltage regulation into SoC package (integrated IVR power chiplets) significantly improves power delivery efficiency making it a must-have piece in the AI infrastructure stack.

The trajectory of integrating more HBM, IO, and GPU in a much larger substrate further increases the urgency of adopting IVR power chiplets. This power delivery architecture shortens the high-current, low-voltage delivery path, reduces conduction loss and voltage droop, improves transient response, and enables finer-grained power management across heterogeneous compute, memory, and IO domains. In AI data centers, IVR power chiplets increase performance per watt, reduce thermal burden, free up valuable board area, and support higher accelerator density within existing rack power and cooling constraints.

The key technical attributes of SoC package integrable IVR power chiplet will be illustrated, including the need of an on-chip magnetic film and a new high frequency voltage regulator circuit.

When IVR power chiplet integrated in SoC package becomes the de facto last stage voltage regulation architecture for AI data center power delivery, the voltage conversion from 800V DC rack power can be partitioned using more optimized high efficiency up-stream conversion stages coupled with high regulation bandwidth IVR power chiplets. This can further enable energy savings at rack and data center level.

Lastly, we introduce the Powerlattice PL1816 chiplet showing that the monolithic IVR power chiplet is already a reality.

Key Technologies Covered

Power Delivery
AI Processors
xPU, GPU, CPU
High-Performance Compute
Data Center Processors
Integrated Voltage Regulation
2.5D, 3D Packaging
Power Distribution Network
Vertical Power Delivery

Featured Speakers

Mr. Sujith Dermal

Co-Founder, Powerlattice Technologies Incorporated

Sujith Dermal is one of the co-founders at Powerlattice. He brings over 15 years of experience in RF, analog and mixed-signal IC product design. At Powerlattice, he leads the systems and customer solutions team to drive the adoption and design of the groundbreaking power delivery chiplet solution. Prior to co-founding the company, he held senior technical roles at Qualcomm/NUVIA, Dialog and Freescale, where he made key contributions to IVR chiplet development and high-volume RF SoC products.

His expertise spans in circuit design, system integration, validation and customer enablement. He is passionate about bridging cutting-edge silicon design with real-world application performance, and has collaborated closely with customers, marketing and manufacturing teams to bring the industry's first power delivery chiplet to the market.