Improving Yield During High Volume Semiconductor Manufacturing Using AI-Coupled, Physics-Based Digital Twins

Process variation and integration sensitivity during high volume semiconductor manufacturing remain major contributors to yield loss. Achieving meaningful yield improvement requires the simultaneous optimization of multiple process steps, design parameters, and manufacturing controls.  However, conventional wafer-based experimentation constrains optimization to serial and isolated parameter changes, making it difficult to diagnose coupled effects and efficiently eliminate multiple yield detractors.

In this presentation, we demonstrate a novel and highly accurate methodology for analyzing and resolving yield limiting issues in high volume manufacturing. The proposed system enables simultaneous evaluation of multiple process changes and supports process retargeting on a nominal fabrication flow. By shifting yield optimization from wafer centric experimentation to a virtual domain, this approach accelerates the reduction and elimination of multiple structural failure modes while significantly reducing wafer-based testing.  The methodology leverages a process virtual twin that integrates physics-based process modeling with machine learning.  This virtual platform enables large scale, multi objective optimization by propagating process variability across complex integration sequences and evaluating its impact on yield critical failure modes.

For illustration, we demonstrate the approach using advanced logic gate all around technology virtual twins built with AI/ML and physics-based process models.  The virtual twins accurately replicate process integration steps, inline and end of line metrology, structural failure mechanisms, and corresponding detection methods.  The results show that a yield optimization platform combining machine learning and physics-based digital twins can simultaneously reduce multiple failure modes, enable rapid yield improvement, and generate optimized, actionable metrology targets for yield engineering teams.  This methodology represents a transformative shift in yield optimization for advanced semiconductor manufacturing, enabling faster path to yield and improved manufacturing readiness at advanced nodes.

Key Technologies Covered 

• Artificial Intelligence and Machine Learning
• Gate-All-Around (GAA) Technology
• Process Variation and Process Integration 
• Digital Twins and Virtual Twins
• High Volume Manufacturing 
• Process Modeling 
• Virtual Metrology 
• Yield Prediction and Improvement
• Multi-Objective Yield Optimization
• Semiconductor Device Modeling