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I/O Infrastructure for Quantum Computing at Scale

10:00 am - 10:30 am

As quantum processors scale toward thousands and eventually millions of qubits, the infrastructure connecting them to room-temperature control and readout electronics increasingly determines how far the system itself can scale. At this scale, channel density, thermal load, signal integrity, reliability, manufacturability and testability must be engineered together.

Integrated, manufacturable interconnect architectures can reduce system complexity while preserving microwave and cryogenic performance. Realizing that benefit requires addressing the trade-offs of high-density routing at the system level, not the component level. Data and examples from Delft Circuits' deployed systems will illustrate the transition from hundreds to thousands of channels, followed by the design principles and integration technologies required for next-generation systems.

Beyond today's systems, moving quantum hardware from bespoke laboratory installations toward repeatable industrial infrastructure will require the materials, processes, packaging and supply-chain capabilities the semiconductor industry has already mastered — and closer collaboration between the two ecosystems to get there faster.

Featured Speakers

Jakob

Dr. Jakob Kammhuber

Chief Technology Officer, Delft Circuits

Dr. Jakob Kammhuber is Chief Technology Officer at Delft Circuits, where he leads R&D and the technology roadmap for high-density cryogenic I/O. Having joined shortly after the company’s founding, he has helped advance its superconducting flexible-interconnect technology from early development toward scalable product platforms for quantum systems. His work focuses on cryogenic signal delivery and the transition from laboratory hardware to industrial-scale quantum systems.

He completed his PhD at QuTech and Delft University of Technology on mesoscopic quantum transport in semiconductor nanostructures, and holds an MSc in Physics from ETH Zürich — a combination that shaped his interest in the engineering challenges of scaling quantum hardware.