Challenge and integrated solution to 3DIC testing

10:40 am - 11:20 am

The booming growth for high-performance computing (HPC) and artificial intelligence (AI) applications has driven significant advancements in packaging technologies. Crucial components such as Known Good Die (KGD) and Known Good Stack (KGS) are essential for the success of 3DFabric™ technology. However, they introduce challenges like increased power consumption, warpage, and thermal management. These challenges necessitate advanced solutions, including cutting-edge probe card design and manufacturing, novel test methodologies, and robust probing infrastructure.

We will present an integrated solution that addresses these challenges, guiding discussions on test coverage strategies—whether to shift left or right—considering the complexities of scrap cost management and the imperative to enhance test coverage. This approach aims to pave the way for revolutionary testability in advanced packaging.

Furthermore, distributed testing methodologies will be introduced to enable rapid yield learning, providing critical information for accelerated yield improvements and improved test coverage to mitigate fab excursions. This comprehensive strategy is poised to realize the full potential of 3DFabric™.

Key Technologies Covered

3DFabric feature and chiplet interconnection, and distributed test.
Testing challenge on thermal management, precise probing, package warpage, etc.
Advanced wafer probing scheme
Integrated testing solution cross test program, probe-card, prober and handler
Testing for yield. Testing for reliability
New test approach SSN, HSIO test
Shift left, shift right test strategy

Featured Speakers

Mr. Chris Wang

Department Manager, TSMC

Chris Wang is the Department Manager of the Test Program Development Department (TPDD) at Taiwan Semiconductor Manufacturing Company (TSMC), Advanced Package Technology Service. He has over decades of experience in the semiconductor testing industry, specializing in system-on-chip (SOC), radio frequency (RF), and power management integrated circuit (PMIC) test program development. His role demands extensive customer interface to support advanced package testing.

Throughout his career, Chris has accumulated vast experience in various product testing areas, including chip probing (CP), final testing (FT), and system-level testing (SLT). He was granted US patent for an innovative high-performance computing (HPC) testing solution. Chris continues to make contributions to the semiconductor testing industry, leveraging his extensive testing experience to provide comprehensive perspectives on 3DFabric testing.