3D IC Package Verification for Heterogeneous Chiplet Design

Friday, September 20
3:25pm to 3:50pm



3DIC is one of the keys to keep the momentum of Moore’s law. To increase the transistor density in unit volume, chipletswith heterogeneous integration and silicon process are used in package design now. The increasing scale and complexity expose challenges in thislatest design methodology. LVS/DRC is the most critical one. Mentor has worked with tier-1 foundry, design house, and package supplier to offer a design flowensuring chiplet3DIC  success. In this session, we will share the design challenges of3DIC and how Mentor solution help overcome them.

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