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Connecting the SoC to Multi-Chip Integration

Friday, September 20
11:15am to 11:40am

Abstract:

How Moore’s law guides CMOS scaling and goes on doubling transistor density in each generation has been widely discussed and became more and more controversial lately. The keyobstacles in the way to integrate more transistors in a single chip will be introduced from a SoCpoint of view. In the other end, mostly believed heterogeneous integration (HI) or homogeneous integration (HI) through wafer/substrate/package level will soar in the near future. A few SiP examples for connectivity and IoT applications will demonstrate the effectiveness and necessity of such heterogeneous integration.

  Moreover, the limited performance improvement of CMOS scaling and the tremendous computing demand of Cloud/AI application urge the rise and evolution of homogeneous integration. D2D (Die to Die) communication will become a crucial technology and standard to overall eco-system. This may eventually open up a great opportunity of IP business model for semiconductor industry in the future.

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