High performance computing (HPC) has become the most critical platform in the development of process technologies for AI (Artificial intelligence) chips. The cloud computing which requires high memory bandwidth for deep learning and training results in the CoWoS (Chipon Waferon Substrate) emergenceas key packaging processes for such chips since 2014. GUC (Global Unichip Corp.) HBM IP solutions also successfully implemented on 12nm and 7nm AI training chip, respectively.
Looking forward the 5G, IoV (Internet of Vehicle) and Smart City, AI architecture will be blooming not only the upstream cloud computing, but also midstream edge computing. The edge computing AI chips need to be more boosted by upgrading chip design architecture and changing the transistor technology in the front end. GUC Die to Die IP solutions incorporating TSMC advanced InFO (Integrated Fan-Out) technologies also could integrate edge computing AI chips in terms of yield, PPA and time to market challenges.
It will be increasingly challenging for edge computing to integrate SoC (System on Chip) and memory chips on advanced package, such as Die to Die by InFO technologies, GUC believes the join forces with EDA, IP, IC designers and package technology are must to build a complete ecosystem if they want to secure a preemptive presence in the next generation AI era.