Large scale heterogeneous system-on-chip monolithic integration becomes more challenging, technically and economically, with advanced CMOS scaling. Some individual functions for memory storage or logic still benefit significantly from CMOS scaling, but implementation requirements are diverging. A more optimum solution can be realized using a heterogeneous multi-die integration. This however will result in an increasing number of technology choices. Therefore, a system-technology co-optimization (STCO) approach is required.
The impact of multi-die interconnect technology choices need to be integrated in the earliest phases of system (chip) design. 3D integration technologies are the enabling technologies for advanced STCO. Different 3D integration technologies can be applied at different levels of the 3D interconnect hierarchy, from the package to the die, to the wafer, to the standard cell and even to the transistor level, spanning an exponential scale in interconnect density.
In this presentation different approaches to system partitioning, cost impact of partitioning and results of state-of-the-art EDA tools to create a functionally partitioned 3D-SOC systems will be shown. Also the recent developments on advanced 3D integration technologies studied at imec will be highlighted.