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Materials Processing for Scaled Devices

Thursday, September 19
10:00am to 10:25am

Abstract:

Logic devices are getting smaller, and the introduction of 3D architectures that use vertical fins and nanowires in their gate design introduce more complexity to the fabrication process. As technology nodes shrink beyond 10 nm, new materials are required in both FEOL and BEOL processes to enable performance, yield, reliability and cost. Successful implementation of new device architectures, whether they are nanowire transistor structures or high-layer-count 3D NAND memory, can’t be accomplished merely by substituting one material with a higher-performing option. One change has a cascading effect on the entire process. Changing the interconnect metal, for example, may require new barrier films and thus new clean chemistries. And with each chemistry change, advancements in membrane technology for effective filtration are required. Whether it is new metallurgy precursors, effective delivery systems, new cleaning formulations, or new filtration membranes, a holistic solution to address performance, efficiency, reliability, yield, and overall cost of ownership is needed.

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