Ph.D., Electrical Engineering, Stanford U.; BSEE, National Taiwan University (NTU)
- Chair (2013-17) & Managing Board Director (1998-Now), SIA of Taiwan
- Chair (2014-15), WSC (World Semiconductor Council)
- Chair (2009-11) and Board Director / Chair of AP Leadership Council, GSA (Global Semiconductor Alliance)
- Recipient of National Medal of Excellence in Science & Technology in Taiwan
- Recipient of Industry Contribution Award from SEMICON Taiwan 2017
- Authored Technical Papers/Keynotes over 60 and US Patents of 37 Granted & >10 Pending; IEEE Solid-State Circuits Field Award Winner (1998); ISSCC Best Evening Panel/Session Awards (5 Times)
- Outstanding Alumnus of NTU & National Chiao-Tung University (also Chair Professor ‘05-‘07)
- Plenary Speaker: 2004 ISSCC Naming a New Silicon-Centric Heterogeneous Integration for System Chips, 2016 A-SSCC for Silicon4.0 x HI x AI Scaling Down&Up Design Methodology, 2018 IEEE HI Roadmap1st Conference, Stanford SystemX IOE Symposium and EETimes Conference Projecting an Arising PI (Pervasive Intelligences) Era with Perspective Formula for Another Exponential Economic Growth beyond Moore’s Law
- Numerous Technical Breakthroughs
- Invented/Realized the SPT Trench-Cell & the World’s Fastest DRAM (IBM Corporate Award)
- Realize Known-Good-Die RAMs over Flash/SOC-Die to Pioneer 3D Heterogeneous Integration (Best Supplier Award by Intel)
- Realized the World’s First/Smallest 360-Panorama 3D-Depthmap Camera (CES 2019) & 360-Spherical Video Camera (CES 2016)
As a researcher, design architect, entrepreneur and chief executive, Dr. Lu has dedicated his career to the worldwide IC design and semiconductor industry. In addition to Etron Technology, where he serves as Founder, Chair, and CEO, he also co-founded several other notable high-tech companies including Ardentec, Global Unichip and GTBF.
He co-invented and pioneered a 3D-DRAM technology, known as the Substrate-Plate Trench-Capacitor (SPT) cell, along with its associated array architecture, which has been widely used by IBM and its licensees from 4Mb to 1Gb DRAMs and embedded DRAMs worth hundreds of billions of dollars. Dr. Lu designed several High-Speed CMOS DRAM (HSDRAM) chips, all with top world record performance. He was a co-architect leading the 8-inch wafer and DRAM/SRAM/LOGIC technology developments for Taiwan’s semiconductor industry in the early 1990s and also created many Taiwan companies as prominent silicon-chip suppliers. Since 1999 he has pioneered Known-Good-Die Memory Products enabling 3D stacked-die system chips; this work summoned the new rise of an IC Heterogeneous Integration Era as described in his ISSCC-2004 plenary talk, demonstrating a new 3D-IC trend. He was a keynote speaker at the 2016 A-SSCC declaring the Silicon-Age-4.0 Era with a new Virtual Moore’s Law for continual economic growth.
Dr. Lu received his B.S. in Electrical Engineering from National Taiwan University and M.S. and Ph.D. in EE from Stanford University. He holds over 37 granted U.S. patents and has published more than 60 technical papers. He serves or has served as Managing Board Director and was Chairman of TSIA, as Board Member of Global Semiconductor Alliance (GSA) and GSA’s General Chair (2009 to 2011), and Chairman of WSC (World Semiconductor Council) from 2014 to 2015.
He received the Scientific Management Award (2012) from Chinese Society for Management of Technology & Taiwan’s Golden Merchant Award (2007) from General Chamber of Commerce. He is an Outstanding Alumnus of National Taiwan University and National Chiao-Tung University (also Chair Professor ‘05-’07), the recipient of the IEEE 1998 Solid-State Circuits Award and a SEMI Industry Contribution Award in 2017, an IEEE Fellow and a member of NAE (National Academy of Engineering of USA).