System-in-package (SiP) is becoming an increasingly important solution for chip package assembly from applications ranging from mobile to high performance. The use of modules for mobile phones is increasingly important as the industry moves to production of 5G handsets. The complexity of these modules requires design and assembly expertise on a greater scale than seen in the past. Miniaturization remains a major drive for the adoption of SiP. High performance SiP options are often described as heterogeneous integration. Some solutions use die functions are fabricated on the latest nodes, combined with other die fabricated on older less expensive nodes and linked together in the package. Combinations of memory and logic in the same package are increasingly common. For AI accelerators, requiring the highest density interconnect, silicon interposers are often used. An increasing trend is the use of fan-out on substrate with RDL interconnects. While passive silicon interposers are used for many of today’s products, future applications will use active interposers. Die are also partitioned, but designed to function together. This solution is often referred to as “chiplets.” This presentation discusses many packaging options and the reasons for use in each application.