Future device integration schemes in memory and logic devices are getting more and more complex in terms of device scaling by lithography. Therefore, further enhanced device architectures are
gaining importance. One of the integration schemes is the removal of frontside Power Distribution Networks (PDN) on the device backside using fusion bonding for layer transfer. On the other hand, for
future memory integration schemes high density 3D interconnects are realized between bonded wafers.
For these reasons, fusion and hybrid bonding have gained considerably importance for 3D integration between device wafers.
Bondscale enable layer transfer by fusion wafer to wafer bonding. Compatibility with enhanced lithography of bonded substrates, sets stringent requirements for post-bond distortion as well as other
device relevant parameters. In this presentation we will discuss influencing parameters related to wafer to wafer bonding for future device scaling according to the IRDS roadmap.